/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : conn_host_csr_top.h
//[Revision time]   : Wed Aug  8 11:41:44 2018
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2018 Mediatek Incorportion. All rights reserved.

#ifndef __CONN_HOST_CSR_TOP_REGS_H__
#define __CONN_HOST_CSR_TOP_REGS_H__

#include "hal_common.h"

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     CONN_HOST_CSR_TOP CR Definitions                     
//
//****************************************************************************

#define CONN_HOST_CSR_TOP_BASE                                 0x18060000

#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_ADDR                    (CONN_HOST_CSR_TOP_BASE + 0x0000) // 0000
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x0010) // 0010
#define CONN_HOST_CSR_TOP_WF_BAND0_IRQ_STAT_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x0014) // 0014
#define CONN_HOST_CSR_TOP_WF_BAND0_IRQ_ENA_ADDR                (CONN_HOST_CSR_TOP_BASE + 0x0018) // 0018
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x0020) // 0020
#define CONN_HOST_CSR_TOP_WF_BAND1_IRQ_STAT_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x0024) // 0024
#define CONN_HOST_CSR_TOP_WF_BAND1_IRQ_ENA_ADDR                (CONN_HOST_CSR_TOP_BASE + 0x0028) // 0028
#define CONN_HOST_CSR_TOP_BGF_LPCTL_ADDR                       (CONN_HOST_CSR_TOP_BASE + 0x0030) // 0030
#define CONN_HOST_CSR_TOP_BGF_IRQ_STAT_ADDR                    (CONN_HOST_CSR_TOP_BASE + 0x0034) // 0034
#define CONN_HOST_CSR_TOP_BGF_IRQ_ENA_ADDR                     (CONN_HOST_CSR_TOP_BASE + 0x0038) // 0038
#define CONN_HOST_CSR_TOP_MD_LPCTL_ADDR                        (CONN_HOST_CSR_TOP_BASE + 0x0050) // 0050
#define CONN_HOST_CSR_TOP_MD_IRQ_STAT_ADDR                     (CONN_HOST_CSR_TOP_BASE + 0x0054) // 0054
#define CONN_HOST_CSR_TOP_MD_IRQ_ENA_ADDR                      (CONN_HOST_CSR_TOP_BASE + 0x0058) // 0058
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x0090) // 0090
#define CONN_HOST_CSR_TOP_WF_MCU_DBG_IDS_SEL_ADDR              (CONN_HOST_CSR_TOP_BASE + 0x0098) // 0098
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_LOG_SEL_ADDR              (CONN_HOST_CSR_TOP_BASE + 0x00a0) // 00A0
#define CONN_HOST_CSR_TOP_BGF_MCU_DBG_IDS_SEL_ADDR             (CONN_HOST_CSR_TOP_BASE + 0x00a8) // 00A8
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_ADDR                (CONN_HOST_CSR_TOP_BASE + 0x00c0) // 00C0
#define CONN_HOST_CSR_TOP_MESSAGE_WF2AP_ADDR                   (CONN_HOST_CSR_TOP_BASE + 0x00d0) // 00D0
#define CONN_HOST_CSR_TOP_MESSAGE_AP2WF_ADDR                   (CONN_HOST_CSR_TOP_BASE + 0x00d4) // 00D4
#define CONN_HOST_CSR_TOP_MESSAGE_BGF2AP_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x00d8) // 00D8
#define CONN_HOST_CSR_TOP_MESSAGE_AP2BGF_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x00dc) // 00DC
#define CONN_HOST_CSR_TOP_CONN_ON_MISC_ADDR                    (CONN_HOST_CSR_TOP_BASE + 0x00f0) // 00F0
#define CONN_HOST_CSR_TOP_RESERVE_CR_ADDR                      (CONN_HOST_CSR_TOP_BASE + 0x00f4) // 00F4
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_ADDR                    (CONN_HOST_CSR_TOP_BASE + 0x0150) // 0150
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_ADDR_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x0154) // 0154
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_EN_ADDR                 (CONN_HOST_CSR_TOP_BASE + 0x0158) // 0158
#define CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_DEBUGSYS_ADDR    (CONN_HOST_CSR_TOP_BASE + 0x0160) // 0160
#define CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_TO_IO_ADDR       (CONN_HOST_CSR_TOP_BASE + 0x0164) // 0164
#define CONN_HOST_CSR_TOP_HOST_PWA_SLP_PROT_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x0170) // 0170
#define CONN_HOST_CSR_TOP_CONN_INFRA_PWA_SLP_PROT_ADDR         (CONN_HOST_CSR_TOP_BASE + 0x0174) // 0174
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_0_ADDR              (CONN_HOST_CSR_TOP_BASE + 0x0180) // 0180
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_1_ADDR              (CONN_HOST_CSR_TOP_BASE + 0x0184) // 0184
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_2_ADDR              (CONN_HOST_CSR_TOP_BASE + 0x0188) // 0188
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_3_ADDR              (CONN_HOST_CSR_TOP_BASE + 0x018c) // 018C
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_0_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x0190) // 0190
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_1_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x0194) // 0194
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_2_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x0198) // 0198
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_3_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x019c) // 019C
#define CONN_HOST_CSR_TOP_DUMMY_RD_DBG_ADDR                    (CONN_HOST_CSR_TOP_BASE + 0x0200) // 0200
#define CONN_HOST_CSR_TOP_WM_MCU_PC_DBG_ADDR                   (CONN_HOST_CSR_TOP_BASE + 0x0204) // 0204
#define CONN_HOST_CSR_TOP_WM_MCU_GPR_DBG_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x0208) // 0208
#define CONN_HOST_CSR_TOP_WA_MCU_PC_DBG_ADDR                   (CONN_HOST_CSR_TOP_BASE + 0x020c) // 020C
#define CONN_HOST_CSR_TOP_WA_MCU_GPR_DBG_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x0210) // 0210
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ADDR              (CONN_HOST_CSR_TOP_BASE + 0x0214) // 0214
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR                   (CONN_HOST_CSR_TOP_BASE + 0x0218) // 0218
#define CONN_HOST_CSR_TOP_WFSYS_MONFLG_OUT_ADDR                (CONN_HOST_CSR_TOP_BASE + 0x021c) // 021C
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR        (CONN_HOST_CSR_TOP_BASE + 0x0220) // 0220
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_DBG_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x022c) // 022C
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ADDR                    (CONN_HOST_CSR_TOP_BASE + 0x0230) // 0230
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x0234) // 0234
#define CONN_HOST_CSR_TOP_BGFSYS_MONFLG_OUT_ADDR               (CONN_HOST_CSR_TOP_BASE + 0x0238) // 0238
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR       (CONN_HOST_CSR_TOP_BASE + 0x023c) // 023C
#define CONN_HOST_CSR_TOP_WF_MAILBOX_DBG_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x0260) // 0260
#define CONN_HOST_CSR_TOP_N13_MCU_MAILBOX_DBG_ADDR             (CONN_HOST_CSR_TOP_BASE + 0x0264) // 0264
#define CONN_HOST_CSR_TOP_N9_MCU_MAILBOX_DBG_ADDR              (CONN_HOST_CSR_TOP_BASE + 0x0268) // 0268
#define CONN_HOST_CSR_TOP_BT_MAILBOX_DBG_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x026c) // 026C
#define CONN_HOST_CSR_TOP_GPS_MAILBOX_DBG_ADDR                 (CONN_HOST_CSR_TOP_BASE + 0x0270) // 0270
#define CONN_HOST_CSR_TOP_MD_MAILBOX_DBG_ADDR                  (CONN_HOST_CSR_TOP_BASE + 0x0274) // 0274
#define CONN_HOST_CSR_TOP_CONN_HIF_HOST_DEBUG_ADDR             (CONN_HOST_CSR_TOP_BASE + 0x0280) // 0280
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_GLUE_DBG_ADDR            (CONN_HOST_CSR_TOP_BASE + 0x0284) // 0284
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_DBG_ADDR                 (CONN_HOST_CSR_TOP_BASE + 0x0288) // 0288
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_DBG_ADDR            (CONN_HOST_CSR_TOP_BASE + 0x028c) // 028C
#define CONN_HOST_CSR_TOP_CONN_HIF_BUSY_DEBUG_ADDR             (CONN_HOST_CSR_TOP_BASE + 0x0290) // 0290
#define CONN_HOST_CSR_TOP_MONFLAG_DBG_ADDR                     (CONN_HOST_CSR_TOP_BASE + 0x0294) // 0294




/* =====================================================================================

  ---BUS_MCU_STAT (0x18060000 + 0x0000)---

    ap_clk_detect_bus_clr_pulse[0] - (WO) Host set this bit to reset bus detect state
                                     This cr will generate a reset signal for bus clock detecion state
                                     After write 1, you have to write 0 to release reset
    hclk_fr_ck_detect[1]         - (RO) Connsys bus hclk detection status
                                     0 : bus hclk non-alive
                                     1 : bus hclk alive
                                     User could write 1 to clear detection status.
                                     After write 1 clear status and then read back to check clock status. It can check bus hclk alive or not.
    osc_clk_detect[2]            - (RO) Connsys osc clock detection status
                                     0 : osc clock non-alive
                                     1 : osc clock alive
                                     User could write 1 to clear detection status.
                                     After write 1 clear status and then read back to check clock status. It can check osc clock alive or not.
    RESERVED3[13..3]             - (RO) Reserved bits
    bgf_mcu_pwr_stat_is_sleep_sync[14] - (RO) Connsys wf bgfsys bus clock status
                                     0 : mcu bus clock active (mcu active)
                                     1 : mcu bus clock gated (mcu non-active)
    wf_mcu_pwr_stat_is_sleep_sync[15] - (RO) Connsys wf mcusys bus clock status
                                     0 : mcu bus clock active (mcu active)
                                     1 : mcu bus clock gated (mcu non-active)
    conn_host_csr_dbg_sel[23..16] - (RW) debug selection control to host csr top
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_conn_host_csr_dbg_sel_ADDR CONN_HOST_CSR_TOP_BUS_MCU_STAT_ADDR
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_conn_host_csr_dbg_sel_MASK 0x00FF0000                // conn_host_csr_dbg_sel[23..16]
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_conn_host_csr_dbg_sel_SHFT 16
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_wf_mcu_pwr_stat_is_sleep_sync_ADDR CONN_HOST_CSR_TOP_BUS_MCU_STAT_ADDR
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_wf_mcu_pwr_stat_is_sleep_sync_MASK 0x00008000                // wf_mcu_pwr_stat_is_sleep_sync[15]
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_wf_mcu_pwr_stat_is_sleep_sync_SHFT 15
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_bgf_mcu_pwr_stat_is_sleep_sync_ADDR CONN_HOST_CSR_TOP_BUS_MCU_STAT_ADDR
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_bgf_mcu_pwr_stat_is_sleep_sync_MASK 0x00004000                // bgf_mcu_pwr_stat_is_sleep_sync[14]
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_bgf_mcu_pwr_stat_is_sleep_sync_SHFT 14
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_osc_clk_detect_ADDR     CONN_HOST_CSR_TOP_BUS_MCU_STAT_ADDR
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_osc_clk_detect_MASK     0x00000004                // osc_clk_detect[2]
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_osc_clk_detect_SHFT     2
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_hclk_fr_ck_detect_ADDR  CONN_HOST_CSR_TOP_BUS_MCU_STAT_ADDR
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_hclk_fr_ck_detect_MASK  0x00000002                // hclk_fr_ck_detect[1]
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_hclk_fr_ck_detect_SHFT  1
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_ap_clk_detect_bus_clr_pulse_ADDR CONN_HOST_CSR_TOP_BUS_MCU_STAT_ADDR
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_ap_clk_detect_bus_clr_pulse_MASK 0x00000001                // ap_clk_detect_bus_clr_pulse[0]
#define CONN_HOST_CSR_TOP_BUS_MCU_STAT_ap_clk_detect_bus_clr_pulse_SHFT 0

/* =====================================================================================

  ---WF_BAND0_LPCTL (0x18060000 + 0x0010)---

    conn_wf_b0_ap_host_set_fw_own_hs_pulse[0] - (WO) Host set this bit to transfer ownership to FW (WF Band 0). 
                                     This will introduce an interrupt to FW and u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_wf_b0_host_csr_fw_own_sts[0x1800_1404] bit[0] will be set to 1.
    conn_wf_b0_ap_host_clr_fw_own_hs_pulse[1] - (WO) Host set this bit to request ownership back to HOST from FW (WF Band 0). 
                                     This will introduce an interrupt to FW and u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_wf_b0_host_csr_fw_own_sts[0x1800_1404] bit[1] will be set to 1.
    conn_wf_b0_host_lpcr_fw_own_sync[2] - (RO) [WiFi_Driver_Own_DBG] (WF Band 0)
                                     ap host_csr firmware own status (0: driver own, 1:firmware own)
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_conn_wf_b0_host_lpcr_fw_own_sync_ADDR CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_conn_wf_b0_host_lpcr_fw_own_sync_MASK 0x00000004                // conn_wf_b0_host_lpcr_fw_own_sync[2]
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_conn_wf_b0_host_lpcr_fw_own_sync_SHFT 2
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_conn_wf_b0_ap_host_clr_fw_own_hs_pulse_ADDR CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_conn_wf_b0_ap_host_clr_fw_own_hs_pulse_MASK 0x00000002                // conn_wf_b0_ap_host_clr_fw_own_hs_pulse[1]
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_conn_wf_b0_ap_host_clr_fw_own_hs_pulse_SHFT 1
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_conn_wf_b0_ap_host_set_fw_own_hs_pulse_ADDR CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_conn_wf_b0_ap_host_set_fw_own_hs_pulse_MASK 0x00000001                // conn_wf_b0_ap_host_set_fw_own_hs_pulse[0]
#define CONN_HOST_CSR_TOP_WF_BAND0_LPCTL_conn_wf_b0_ap_host_set_fw_own_hs_pulse_SHFT 0

/* =====================================================================================

  ---WF_BAND0_IRQ_STAT (0x18060000 + 0x0014)---

    conn_wf_b0_host_lpcr_fw_own_clr_stat[0] - (W1C) Host AP own interrupt. (cause by WF Band 0)
                                     Write 1 clear interrupt status.
                                     0 : no interrupt
                                     1: host_own interrupt
                                     
                                     When firmware write 1 clear u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_wf_b0_host_lpcr_fw_own [0x1800_1408] bit[0] . Hardware would trigger host side host_own_int. It means firmware transfer ownership to driver.
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_BAND0_IRQ_STAT_conn_wf_b0_host_lpcr_fw_own_clr_stat_ADDR CONN_HOST_CSR_TOP_WF_BAND0_IRQ_STAT_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND0_IRQ_STAT_conn_wf_b0_host_lpcr_fw_own_clr_stat_MASK 0x00000001                // conn_wf_b0_host_lpcr_fw_own_clr_stat[0]
#define CONN_HOST_CSR_TOP_WF_BAND0_IRQ_STAT_conn_wf_b0_host_lpcr_fw_own_clr_stat_SHFT 0

/* =====================================================================================

  ---WF_BAND0_IRQ_ENA (0x18060000 + 0x0018)---

    conn_hif_on_wf_b0_irq_ena[3..0] - (RW) host AP own interrupt enable(only bit0 used) (cause by WF Band 0)
                                     0 : interrupt disable
                                     1 : interrupt enable
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_BAND0_IRQ_ENA_conn_hif_on_wf_b0_irq_ena_ADDR CONN_HOST_CSR_TOP_WF_BAND0_IRQ_ENA_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND0_IRQ_ENA_conn_hif_on_wf_b0_irq_ena_MASK 0x0000000F                // conn_hif_on_wf_b0_irq_ena[3..0]
#define CONN_HOST_CSR_TOP_WF_BAND0_IRQ_ENA_conn_hif_on_wf_b0_irq_ena_SHFT 0

/* =====================================================================================

  ---WF_BAND1_LPCTL (0x18060000 + 0x0020)---

    conn_wf_b1_ap_host_set_fw_own_hs_pulse[0] - (WO) Host set this bit to transfer ownership to FW (WF Band 1). 
                                     This will introduce an interrupt to FW and u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_wf_b1_host_csr_fw_own_sts[0x1800_140C] bit[0] will be set to 1.
    conn_wf_b1_ap_host_clr_fw_own_hs_pulse[1] - (WO) Host set this bit to request ownership back to HOST from FW (WF Band 1). 
                                     This will introduce an interrupt to FW and u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_wf_b1_host_csr_fw_own_sts[0x1800_140C] bit[1] will be set to 1.
    conn_wf_b1_host_lpcr_fw_own_sync[2] - (RO) [WiFi_Driver_Own_DBG] (WF Band 1)
                                     ap host_csr firmware own status (0: driver own, 1:firmware own)
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_conn_wf_b1_host_lpcr_fw_own_sync_ADDR CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_conn_wf_b1_host_lpcr_fw_own_sync_MASK 0x00000004                // conn_wf_b1_host_lpcr_fw_own_sync[2]
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_conn_wf_b1_host_lpcr_fw_own_sync_SHFT 2
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_conn_wf_b1_ap_host_clr_fw_own_hs_pulse_ADDR CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_conn_wf_b1_ap_host_clr_fw_own_hs_pulse_MASK 0x00000002                // conn_wf_b1_ap_host_clr_fw_own_hs_pulse[1]
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_conn_wf_b1_ap_host_clr_fw_own_hs_pulse_SHFT 1
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_conn_wf_b1_ap_host_set_fw_own_hs_pulse_ADDR CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_conn_wf_b1_ap_host_set_fw_own_hs_pulse_MASK 0x00000001                // conn_wf_b1_ap_host_set_fw_own_hs_pulse[0]
#define CONN_HOST_CSR_TOP_WF_BAND1_LPCTL_conn_wf_b1_ap_host_set_fw_own_hs_pulse_SHFT 0

/* =====================================================================================

  ---WF_BAND1_IRQ_STAT (0x18060000 + 0x0024)---

    conn_wf_b1_host_lpcr_fw_own_clr_stat[0] - (W1C) Host AP own interrupt. (cause by WF Band 1)
                                     Write 1 clear interrupt status.
                                     0 : no interrupt
                                     1: host_own interrupt
                                     
                                     When firmware write 1 clear u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_wf_b1_host_lpcr_fw_own [0x1800_1410] bit[0] . Hardware would trigger host side host_own_int. It means firmware transfer ownership to driver.
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_BAND1_IRQ_STAT_conn_wf_b1_host_lpcr_fw_own_clr_stat_ADDR CONN_HOST_CSR_TOP_WF_BAND1_IRQ_STAT_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND1_IRQ_STAT_conn_wf_b1_host_lpcr_fw_own_clr_stat_MASK 0x00000001                // conn_wf_b1_host_lpcr_fw_own_clr_stat[0]
#define CONN_HOST_CSR_TOP_WF_BAND1_IRQ_STAT_conn_wf_b1_host_lpcr_fw_own_clr_stat_SHFT 0

/* =====================================================================================

  ---WF_BAND1_IRQ_ENA (0x18060000 + 0x0028)---

    conn_hif_on_wf_b1_irq_ena[3..0] - (RW) host AP own interrupt enable(only bit0 used) (cause by WF Band 1)
                                     0 : interrupt disable
                                     1 : interrupt enable
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_BAND1_IRQ_ENA_conn_hif_on_wf_b1_irq_ena_ADDR CONN_HOST_CSR_TOP_WF_BAND1_IRQ_ENA_ADDR
#define CONN_HOST_CSR_TOP_WF_BAND1_IRQ_ENA_conn_hif_on_wf_b1_irq_ena_MASK 0x0000000F                // conn_hif_on_wf_b1_irq_ena[3..0]
#define CONN_HOST_CSR_TOP_WF_BAND1_IRQ_ENA_conn_hif_on_wf_b1_irq_ena_SHFT 0

/* =====================================================================================

  ---BGF_LPCTL (0x18060000 + 0x0030)---

    conn_bgf_ap_host_set_fw_own_hs_pulse[0] - (WO) Host set this bit to transfer ownership to FW (WF Band 1). 
                                     This will introduce an interrupt to FW and u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_bgf_host_csr_fw_own_sts[0x1800_141C] bit[0] will be set to 1.
    conn_bgf_ap_host_clr_fw_own_hs_pulse[1] - (WO) Host set this bit to request ownership back to HOST from FW (BGF). 
                                     This will introduce an interrupt to FW and u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_bgf_host_csr_fw_own_sts[0x1800_141C] bit[1] will be set to 1.
    conn_bgf_host_lpcr_fw_own_sync[2] - (RO) [BGF_Driver_Own_DBG] 
                                     ap host_csr firmware own status (0: driver own, 1:firmware own)
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_LPCTL_conn_bgf_host_lpcr_fw_own_sync_ADDR CONN_HOST_CSR_TOP_BGF_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_BGF_LPCTL_conn_bgf_host_lpcr_fw_own_sync_MASK 0x00000004                // conn_bgf_host_lpcr_fw_own_sync[2]
#define CONN_HOST_CSR_TOP_BGF_LPCTL_conn_bgf_host_lpcr_fw_own_sync_SHFT 2
#define CONN_HOST_CSR_TOP_BGF_LPCTL_conn_bgf_ap_host_clr_fw_own_hs_pulse_ADDR CONN_HOST_CSR_TOP_BGF_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_BGF_LPCTL_conn_bgf_ap_host_clr_fw_own_hs_pulse_MASK 0x00000002                // conn_bgf_ap_host_clr_fw_own_hs_pulse[1]
#define CONN_HOST_CSR_TOP_BGF_LPCTL_conn_bgf_ap_host_clr_fw_own_hs_pulse_SHFT 1
#define CONN_HOST_CSR_TOP_BGF_LPCTL_conn_bgf_ap_host_set_fw_own_hs_pulse_ADDR CONN_HOST_CSR_TOP_BGF_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_BGF_LPCTL_conn_bgf_ap_host_set_fw_own_hs_pulse_MASK 0x00000001                // conn_bgf_ap_host_set_fw_own_hs_pulse[0]
#define CONN_HOST_CSR_TOP_BGF_LPCTL_conn_bgf_ap_host_set_fw_own_hs_pulse_SHFT 0

/* =====================================================================================

  ---BGF_IRQ_STAT (0x18060000 + 0x0034)---

    conn_bgf_host_lpcr_fw_own_clr_stat[0] - (W1C) Host AP own interrupt. (cause by BGF)
                                     Write 1 clear interrupt status.
                                     0 : no interrupt
                                     1: host_own interrupt
                                     
                                     When firmware write 1 clear u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_bgf_host_lpcr_fw_own [0x1800_1420] bit[0] . Hardware would trigger host side host_own_int. It means firmware transfer ownership to driver.
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_IRQ_STAT_conn_bgf_host_lpcr_fw_own_clr_stat_ADDR CONN_HOST_CSR_TOP_BGF_IRQ_STAT_ADDR
#define CONN_HOST_CSR_TOP_BGF_IRQ_STAT_conn_bgf_host_lpcr_fw_own_clr_stat_MASK 0x00000001                // conn_bgf_host_lpcr_fw_own_clr_stat[0]
#define CONN_HOST_CSR_TOP_BGF_IRQ_STAT_conn_bgf_host_lpcr_fw_own_clr_stat_SHFT 0

/* =====================================================================================

  ---BGF_IRQ_ENA (0x18060000 + 0x0038)---

    conn_hif_on_bgf_irq_ena[3..0] - (RW) host AP own interrupt enable(only bit0 used) (cause by BGF)
                                     0 : interrupt disable
                                     1 : interrupt enable
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_IRQ_ENA_conn_hif_on_bgf_irq_ena_ADDR CONN_HOST_CSR_TOP_BGF_IRQ_ENA_ADDR
#define CONN_HOST_CSR_TOP_BGF_IRQ_ENA_conn_hif_on_bgf_irq_ena_MASK 0x0000000F                // conn_hif_on_bgf_irq_ena[3..0]
#define CONN_HOST_CSR_TOP_BGF_IRQ_ENA_conn_hif_on_bgf_irq_ena_SHFT 0

/* =====================================================================================

  ---MD_LPCTL (0x18060000 + 0x0050)---

    conn_md_host_set_fw_own_hs_pulse[0] - (WO) Host set this bit to transfer ownership to FW. 
                                     This will introduce an interrupt to FW and u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_md_host_csr_fw_own_sts[0x1800_1414] bit[0] will be set to 1.
    conn_md_host_clr_fw_own_hs_pulse[1] - (WO) Host set this bit to request ownership back to HOST from FW. 
                                     This will introduce an interrupt to FW and u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_md_host_csr_fw_own_sts[0x1800_1414] bit[1] will be set to 1.
    conn_md_host_lpcr_fw_own_sync[2] - (RO) [MD_Driver_Own_DBG] 
                                     ap host_csr firmware own status (0: driver own, 1:firmware own)
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MD_LPCTL_conn_md_host_lpcr_fw_own_sync_ADDR CONN_HOST_CSR_TOP_MD_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_MD_LPCTL_conn_md_host_lpcr_fw_own_sync_MASK 0x00000004                // conn_md_host_lpcr_fw_own_sync[2]
#define CONN_HOST_CSR_TOP_MD_LPCTL_conn_md_host_lpcr_fw_own_sync_SHFT 2
#define CONN_HOST_CSR_TOP_MD_LPCTL_conn_md_host_clr_fw_own_hs_pulse_ADDR CONN_HOST_CSR_TOP_MD_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_MD_LPCTL_conn_md_host_clr_fw_own_hs_pulse_MASK 0x00000002                // conn_md_host_clr_fw_own_hs_pulse[1]
#define CONN_HOST_CSR_TOP_MD_LPCTL_conn_md_host_clr_fw_own_hs_pulse_SHFT 1
#define CONN_HOST_CSR_TOP_MD_LPCTL_conn_md_host_set_fw_own_hs_pulse_ADDR CONN_HOST_CSR_TOP_MD_LPCTL_ADDR
#define CONN_HOST_CSR_TOP_MD_LPCTL_conn_md_host_set_fw_own_hs_pulse_MASK 0x00000001                // conn_md_host_set_fw_own_hs_pulse[0]
#define CONN_HOST_CSR_TOP_MD_LPCTL_conn_md_host_set_fw_own_hs_pulse_SHFT 0

/* =====================================================================================

  ---MD_IRQ_STAT (0x18060000 + 0x0054)---

    conn_md_lpcr_fw_own_clr_stat[0] - (W1C) Host Modem own interrupt.
                                     Write 1 clear interrupt status.
                                     0 : no interrupt
                                     1: host_own interrupt
                                     
                                     When firmware write 1 clear u_conn_infra_cfg.u_conn_infra_csr_ctrl.conn_md_host_lpcr_fw_own [0x1800_1418] bit[0] . Hardware would trigger host side host_own_int. It means firmware transfer ownership to driver.
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MD_IRQ_STAT_conn_md_lpcr_fw_own_clr_stat_ADDR CONN_HOST_CSR_TOP_MD_IRQ_STAT_ADDR
#define CONN_HOST_CSR_TOP_MD_IRQ_STAT_conn_md_lpcr_fw_own_clr_stat_MASK 0x00000001                // conn_md_lpcr_fw_own_clr_stat[0]
#define CONN_HOST_CSR_TOP_MD_IRQ_STAT_conn_md_lpcr_fw_own_clr_stat_SHFT 0

/* =====================================================================================

  ---MD_IRQ_ENA (0x18060000 + 0x0058)---

    conn_hif_on_md_irq_ena[3..0] - (RW) host Modem own interrupt enable(only bit0 used)
                                     0 : interrupt disable
                                     1 : interrupt enable
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MD_IRQ_ENA_conn_hif_on_md_irq_ena_ADDR CONN_HOST_CSR_TOP_MD_IRQ_ENA_ADDR
#define CONN_HOST_CSR_TOP_MD_IRQ_ENA_conn_hif_on_md_irq_ena_MASK 0x0000000F                // conn_hif_on_md_irq_ena[3..0]
#define CONN_HOST_CSR_TOP_MD_IRQ_ENA_conn_hif_on_md_irq_ena_SHFT 0

/* =====================================================================================

  ---WF_MCU_PC_LOG_SEL (0x18060000 + 0x0090)---

    wf_rg_mcu_pwr_stat_chk_disable[0] - (RW) ap2conn axi bus was protect by mcu_pwr_stat to prevent bus hang.
                                     Mcu_pwr_sta_chk_disable was used for debug. When this register was set, mcu_pwr_stat protect would be disable.
    RESERVED1[1]                 - (RO) Reserved bits
    conn_wf_wm_mcu_dbg_pc_log_sel[7..2] - (RW) Mcusys wm_dbg_pc_log selection.
                                     The mcu_dbg_pc_log can be read on conn_hif_on_dbgcr01
    conn_wf_wm_mcu_dbg_gpr_log_sel[13..8] - (RW) Mcusys  wm_dbg_gpr_log selection.
                                     The mcu_dbg_pc_log can be read on conn_hif_on_dbgcr02
    conn_wf_wa_mcu_dbg_pc_log_sel[19..14] - (RW) Mcusys wa_dbg_pc_log selection.
                                     The mcu_dbg_pc_log can be read on conn_hif_on_dbgcr03
    conn_wf_wa_mcu_dbg_gpr_log_sel[25..20] - (RW) Mcusys wa_dbg_gpr_log selection.
                                     The mcu_dbg_pc_log can be read on conn_hif_on_dbgcr04
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wa_mcu_dbg_gpr_log_sel_ADDR CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_ADDR
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wa_mcu_dbg_gpr_log_sel_MASK 0x03F00000                // conn_wf_wa_mcu_dbg_gpr_log_sel[25..20]
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wa_mcu_dbg_gpr_log_sel_SHFT 20
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wa_mcu_dbg_pc_log_sel_ADDR CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_ADDR
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wa_mcu_dbg_pc_log_sel_MASK 0x000FC000                // conn_wf_wa_mcu_dbg_pc_log_sel[19..14]
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wa_mcu_dbg_pc_log_sel_SHFT 14
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wm_mcu_dbg_gpr_log_sel_ADDR CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_ADDR
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wm_mcu_dbg_gpr_log_sel_MASK 0x00003F00                // conn_wf_wm_mcu_dbg_gpr_log_sel[13..8]
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wm_mcu_dbg_gpr_log_sel_SHFT 8
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wm_mcu_dbg_pc_log_sel_ADDR CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_ADDR
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wm_mcu_dbg_pc_log_sel_MASK 0x000000FC                // conn_wf_wm_mcu_dbg_pc_log_sel[7..2]
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_conn_wf_wm_mcu_dbg_pc_log_sel_SHFT 2
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_wf_rg_mcu_pwr_stat_chk_disable_ADDR CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_ADDR
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_wf_rg_mcu_pwr_stat_chk_disable_MASK 0x00000001                // wf_rg_mcu_pwr_stat_chk_disable[0]
#define CONN_HOST_CSR_TOP_WF_MCU_PC_LOG_SEL_wf_rg_mcu_pwr_stat_chk_disable_SHFT 0

/* =====================================================================================

  ---WF_MCU_DBG_IDS_SEL (0x18060000 + 0x0098)---

    conn_wf_mcu_dbg_ids_sel[31..0] - (RW)  xxx 

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_MCU_DBG_IDS_SEL_conn_wf_mcu_dbg_ids_sel_ADDR CONN_HOST_CSR_TOP_WF_MCU_DBG_IDS_SEL_ADDR
#define CONN_HOST_CSR_TOP_WF_MCU_DBG_IDS_SEL_conn_wf_mcu_dbg_ids_sel_MASK 0xFFFFFFFF                // conn_wf_mcu_dbg_ids_sel[31..0]
#define CONN_HOST_CSR_TOP_WF_MCU_DBG_IDS_SEL_conn_wf_mcu_dbg_ids_sel_SHFT 0

/* =====================================================================================

  ---BGF_MCU_PC_LOG_SEL (0x18060000 + 0x00a0)---

    bgf_rg_mcu_pwr_stat_chk_disable[0] - (RW) ap2conn axi bus was protect by mcu_pwr_stat to prevent bus hang.
                                     Mcu_pwr_sta_chk_disable was used for debug. When this register was set, mcu_pwr_stat protect would be disable.
    RESERVED1[1]                 - (RO) Reserved bits
    conn_bgf_mcu_dbg_pc_log_sel[7..2] - (RW) Mcusys bgf_dbg_pc_log selection.
                                     The mcu_dbg_pc_log can be read on conn_hif_on_dbgcr11
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_LOG_SEL_conn_bgf_mcu_dbg_pc_log_sel_ADDR CONN_HOST_CSR_TOP_BGF_MCU_PC_LOG_SEL_ADDR
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_LOG_SEL_conn_bgf_mcu_dbg_pc_log_sel_MASK 0x000000FC                // conn_bgf_mcu_dbg_pc_log_sel[7..2]
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_LOG_SEL_conn_bgf_mcu_dbg_pc_log_sel_SHFT 2
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_LOG_SEL_bgf_rg_mcu_pwr_stat_chk_disable_ADDR CONN_HOST_CSR_TOP_BGF_MCU_PC_LOG_SEL_ADDR
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_LOG_SEL_bgf_rg_mcu_pwr_stat_chk_disable_MASK 0x00000001                // bgf_rg_mcu_pwr_stat_chk_disable[0]
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_LOG_SEL_bgf_rg_mcu_pwr_stat_chk_disable_SHFT 0

/* =====================================================================================

  ---BGF_MCU_DBG_IDS_SEL (0x18060000 + 0x00a8)---

    conn_bgf_mcu_dbg_ids_sel[31..0] - (RW)  xxx 

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_MCU_DBG_IDS_SEL_conn_bgf_mcu_dbg_ids_sel_ADDR CONN_HOST_CSR_TOP_BGF_MCU_DBG_IDS_SEL_ADDR
#define CONN_HOST_CSR_TOP_BGF_MCU_DBG_IDS_SEL_conn_bgf_mcu_dbg_ids_sel_MASK 0xFFFFFFFF                // conn_bgf_mcu_dbg_ids_sel[31..0]
#define CONN_HOST_CSR_TOP_BGF_MCU_DBG_IDS_SEL_conn_bgf_mcu_dbg_ids_sel_SHFT 0

/* =====================================================================================

  ---CONN_HIF_ON_MISC (0x18060000 + 0x00c0)---

    rg_ap2conn_clk_always_on[0]  - (RW) Internal design option. User could not write this register.
                                     Ap2conn_ahb_idle was used to control ap_hclk. This design option could always enable ap2conn_hclk for debug usage
                                     0 : default
                                     1 : always turn on ap2conn_hclk
    rg_ap2conn_debounce_disable[1] - (RW) Internal design option. User could not write this register.
                                     Disable ap2conn_ahb_idle debound function. It can request more ap2conn_hclk in debounce period.
                                     0 : enable debounce function
                                     1 : disable debounce function
    rg_ap2conn_idle_debounce_th[7..2] - (RW) idle detect debounce counter threshhold
    rg_ap2conn_dcm_slp_ctl[9..8] - (RW) AP_CLK DCM function
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_dcm_slp_ctl_ADDR CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_ADDR
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_dcm_slp_ctl_MASK 0x00000300                // rg_ap2conn_dcm_slp_ctl[9..8]
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_dcm_slp_ctl_SHFT 8
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_idle_debounce_th_ADDR CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_ADDR
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_idle_debounce_th_MASK 0x000000FC                // rg_ap2conn_idle_debounce_th[7..2]
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_idle_debounce_th_SHFT 2
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_debounce_disable_ADDR CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_ADDR
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_debounce_disable_MASK 0x00000002                // rg_ap2conn_debounce_disable[1]
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_debounce_disable_SHFT 1
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_clk_always_on_ADDR CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_ADDR
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_clk_always_on_MASK 0x00000001                // rg_ap2conn_clk_always_on[0]
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_rg_ap2conn_clk_always_on_SHFT 0

/* =====================================================================================

  ---MESSAGE_WF2AP (0x18060000 + 0x00d0)---

    cr_wf2ap_host_on_cfg[15..0]  - (RO) This register could be set by firmware(WF) and read by host.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MESSAGE_WF2AP_cr_wf2ap_host_on_cfg_ADDR CONN_HOST_CSR_TOP_MESSAGE_WF2AP_ADDR
#define CONN_HOST_CSR_TOP_MESSAGE_WF2AP_cr_wf2ap_host_on_cfg_MASK 0x0000FFFF                // cr_wf2ap_host_on_cfg[15..0]
#define CONN_HOST_CSR_TOP_MESSAGE_WF2AP_cr_wf2ap_host_on_cfg_SHFT 0

/* =====================================================================================

  ---MESSAGE_AP2WF (0x18060000 + 0x00d4)---

    cr_ap2wf_host_on_cfg[15..0]  - (RW) This register could be set by host and read by firmware(WF).
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MESSAGE_AP2WF_cr_ap2wf_host_on_cfg_ADDR CONN_HOST_CSR_TOP_MESSAGE_AP2WF_ADDR
#define CONN_HOST_CSR_TOP_MESSAGE_AP2WF_cr_ap2wf_host_on_cfg_MASK 0x0000FFFF                // cr_ap2wf_host_on_cfg[15..0]
#define CONN_HOST_CSR_TOP_MESSAGE_AP2WF_cr_ap2wf_host_on_cfg_SHFT 0

/* =====================================================================================

  ---MESSAGE_BGF2AP (0x18060000 + 0x00d8)---

    cr_bgf2ap_host_on_cfg[15..0] - (RO) This register could be set by firmware(BGF) and read by host.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MESSAGE_BGF2AP_cr_bgf2ap_host_on_cfg_ADDR CONN_HOST_CSR_TOP_MESSAGE_BGF2AP_ADDR
#define CONN_HOST_CSR_TOP_MESSAGE_BGF2AP_cr_bgf2ap_host_on_cfg_MASK 0x0000FFFF                // cr_bgf2ap_host_on_cfg[15..0]
#define CONN_HOST_CSR_TOP_MESSAGE_BGF2AP_cr_bgf2ap_host_on_cfg_SHFT 0

/* =====================================================================================

  ---MESSAGE_AP2BGF (0x18060000 + 0x00dc)---

    cr_ap2bgf_host_on_cfg[15..0] - (RW) This register could be set by host and read by firmware(BGF).
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MESSAGE_AP2BGF_cr_ap2bgf_host_on_cfg_ADDR CONN_HOST_CSR_TOP_MESSAGE_AP2BGF_ADDR
#define CONN_HOST_CSR_TOP_MESSAGE_AP2BGF_cr_ap2bgf_host_on_cfg_MASK 0x0000FFFF                // cr_ap2bgf_host_on_cfg[15..0]
#define CONN_HOST_CSR_TOP_MESSAGE_AP2BGF_cr_ap2bgf_host_on_cfg_SHFT 0

/* =====================================================================================

  ---CONN_ON_MISC (0x18060000 + 0x00f0)---

    drv_fw_stat_sync[2..0]       - (RW)  xxx 
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_ON_MISC_drv_fw_stat_sync_ADDR   CONN_HOST_CSR_TOP_CONN_ON_MISC_ADDR
#define CONN_HOST_CSR_TOP_CONN_ON_MISC_drv_fw_stat_sync_MASK   0x00000007                // drv_fw_stat_sync[2..0]
#define CONN_HOST_CSR_TOP_CONN_ON_MISC_drv_fw_stat_sync_SHFT   0

/* =====================================================================================

  ---RESERVE_CR (0x18060000 + 0x00f4)---

    conn_hif_on_rsv0[31..0]      - (RW) reserved cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_RESERVE_CR_conn_hif_on_rsv0_ADDR     CONN_HOST_CSR_TOP_RESERVE_CR_ADDR
#define CONN_HOST_CSR_TOP_RESERVE_CR_conn_hif_on_rsv0_MASK     0xFFFFFFFF                // conn_hif_on_rsv0[31..0]
#define CONN_HOST_CSR_TOP_RESERVE_CR_conn_hif_on_rsv0_SHFT     0

/* =====================================================================================

  ---CSR_DEADFEED (0x18060000 + 0x0150)---

    cr_host_csr_deadfeed[31..0]  - (RO) Conn host clock domain deadfeed cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_cr_host_csr_deadfeed_ADDR CONN_HOST_CSR_TOP_CSR_DEADFEED_ADDR
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_cr_host_csr_deadfeed_MASK 0xFFFFFFFF                // cr_host_csr_deadfeed[31..0]
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_cr_host_csr_deadfeed_SHFT 0

/* =====================================================================================

  ---CSR_DEADFEED_ADDR (0x18060000 + 0x0154)---

    cr_host_csr_deadfeed_addr[31..0] - (RW) Conn host clock domain deadfeed cr address

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_ADDR_cr_host_csr_deadfeed_addr_ADDR CONN_HOST_CSR_TOP_CSR_DEADFEED_ADDR_ADDR
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_ADDR_cr_host_csr_deadfeed_addr_MASK 0xFFFFFFFF                // cr_host_csr_deadfeed_addr[31..0]
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_ADDR_cr_host_csr_deadfeed_addr_SHFT 0

/* =====================================================================================

  ---CSR_DEADFEED_EN (0x18060000 + 0x0158)---

    cr_host_csr_deadfeed_en[4..0] - (RW) [0] deadfeed en
                                     [1] osc_rdy en
                                     [2] reserved
                                     [3] reserved
                                     [4] force deadfeed en
                                     0 : disable
                                     1 : enable
    RESERVED5[31..5]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_EN_cr_host_csr_deadfeed_en_ADDR CONN_HOST_CSR_TOP_CSR_DEADFEED_EN_ADDR
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_EN_cr_host_csr_deadfeed_en_MASK 0x0000001F                // cr_host_csr_deadfeed_en[4..0]
#define CONN_HOST_CSR_TOP_CSR_DEADFEED_EN_cr_host_csr_deadfeed_en_SHFT 0

/* =====================================================================================

  ---CONN_INFRA_DEBUG_AO_DEBUGSYS (0x18060000 + 0x0160)---

    conn_infra_debug_ctrl_ao_debugsys_ctrl[31..0] - (RW) conn infra bus debug contrl ao debugsys control

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_DEBUGSYS_conn_infra_debug_ctrl_ao_debugsys_ctrl_ADDR CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_DEBUGSYS_ADDR
#define CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_DEBUGSYS_conn_infra_debug_ctrl_ao_debugsys_ctrl_MASK 0xFFFFFFFF                // conn_infra_debug_ctrl_ao_debugsys_ctrl[31..0]
#define CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_DEBUGSYS_conn_infra_debug_ctrl_ao_debugsys_ctrl_SHFT 0

/* =====================================================================================

  ---CONN_INFRA_DEBUG_AO_TO_IO (0x18060000 + 0x0164)---

    conn_infra_debug_ctrl_ao_to_io_ctrl[7..0] - (RW) conn infra bus debug contrl ao to io
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_TO_IO_conn_infra_debug_ctrl_ao_to_io_ctrl_ADDR CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_TO_IO_ADDR
#define CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_TO_IO_conn_infra_debug_ctrl_ao_to_io_ctrl_MASK 0x000000FF                // conn_infra_debug_ctrl_ao_to_io_ctrl[7..0]
#define CONN_HOST_CSR_TOP_CONN_INFRA_DEBUG_AO_TO_IO_conn_infra_debug_ctrl_ao_to_io_ctrl_SHFT 0

/* =====================================================================================

  ---HOST_PWA_SLP_PROT (0x18060000 + 0x0170)---

    conn_host_pwa_pwr_prot_req[0] - (RW) conn infra bus host domain sleep protect req
    conn_host_pwa_pwr_prot_ack[1] - (RO) conn infra bus host domain sleep protect ack
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_HOST_PWA_SLP_PROT_conn_host_pwa_pwr_prot_ack_ADDR CONN_HOST_CSR_TOP_HOST_PWA_SLP_PROT_ADDR
#define CONN_HOST_CSR_TOP_HOST_PWA_SLP_PROT_conn_host_pwa_pwr_prot_ack_MASK 0x00000002                // conn_host_pwa_pwr_prot_ack[1]
#define CONN_HOST_CSR_TOP_HOST_PWA_SLP_PROT_conn_host_pwa_pwr_prot_ack_SHFT 1
#define CONN_HOST_CSR_TOP_HOST_PWA_SLP_PROT_conn_host_pwa_pwr_prot_req_ADDR CONN_HOST_CSR_TOP_HOST_PWA_SLP_PROT_ADDR
#define CONN_HOST_CSR_TOP_HOST_PWA_SLP_PROT_conn_host_pwa_pwr_prot_req_MASK 0x00000001                // conn_host_pwa_pwr_prot_req[0]
#define CONN_HOST_CSR_TOP_HOST_PWA_SLP_PROT_conn_host_pwa_pwr_prot_req_SHFT 0

/* =====================================================================================

  ---CONN_INFRA_PWA_SLP_PROT (0x18060000 + 0x0174)---

    conn_infra_pwa_pwr_prot_req[0] - (RW) conn infra bus infra domain sleep protect req
    conn_infra_pwa_pwr_prot_ack[1] - (RO) conn infra bus infra domain sleep protect ack
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_INFRA_PWA_SLP_PROT_conn_infra_pwa_pwr_prot_ack_ADDR CONN_HOST_CSR_TOP_CONN_INFRA_PWA_SLP_PROT_ADDR
#define CONN_HOST_CSR_TOP_CONN_INFRA_PWA_SLP_PROT_conn_infra_pwa_pwr_prot_ack_MASK 0x00000002                // conn_infra_pwa_pwr_prot_ack[1]
#define CONN_HOST_CSR_TOP_CONN_INFRA_PWA_SLP_PROT_conn_infra_pwa_pwr_prot_ack_SHFT 1
#define CONN_HOST_CSR_TOP_CONN_INFRA_PWA_SLP_PROT_conn_infra_pwa_pwr_prot_req_ADDR CONN_HOST_CSR_TOP_CONN_INFRA_PWA_SLP_PROT_ADDR
#define CONN_HOST_CSR_TOP_CONN_INFRA_PWA_SLP_PROT_conn_infra_pwa_pwr_prot_req_MASK 0x00000001                // conn_infra_pwa_pwr_prot_req[0]
#define CONN_HOST_CSR_TOP_CONN_INFRA_PWA_SLP_PROT_conn_infra_pwa_pwr_prot_req_SHFT 0

/* =====================================================================================

  ---BGF_CSR_DUMMY_CR_0 (0x18060000 + 0x0180)---

    conn_bgf_host_csr_dummy_0[31..0] - (RW) reserved cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_0_conn_bgf_host_csr_dummy_0_ADDR CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_0_ADDR
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_0_conn_bgf_host_csr_dummy_0_MASK 0xFFFFFFFF                // conn_bgf_host_csr_dummy_0[31..0]
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_0_conn_bgf_host_csr_dummy_0_SHFT 0

/* =====================================================================================

  ---BGF_CSR_DUMMY_CR_1 (0x18060000 + 0x0184)---

    conn_bgf_host_csr_dummy_1[31..0] - (RW) reserved cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_1_conn_bgf_host_csr_dummy_1_ADDR CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_1_ADDR
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_1_conn_bgf_host_csr_dummy_1_MASK 0xFFFFFFFF                // conn_bgf_host_csr_dummy_1[31..0]
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_1_conn_bgf_host_csr_dummy_1_SHFT 0

/* =====================================================================================

  ---BGF_CSR_DUMMY_CR_2 (0x18060000 + 0x0188)---

    conn_bgf_host_csr_dummy_2[31..0] - (RW) reserved cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_2_conn_bgf_host_csr_dummy_2_ADDR CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_2_ADDR
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_2_conn_bgf_host_csr_dummy_2_MASK 0xFFFFFFFF                // conn_bgf_host_csr_dummy_2[31..0]
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_2_conn_bgf_host_csr_dummy_2_SHFT 0

/* =====================================================================================

  ---BGF_CSR_DUMMY_CR_3 (0x18060000 + 0x018c)---

    conn_bgf_host_csr_dummy_3[31..0] - (RW) reserved cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_3_conn_bgf_host_csr_dummy_3_ADDR CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_3_ADDR
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_3_conn_bgf_host_csr_dummy_3_MASK 0xFFFFFFFF                // conn_bgf_host_csr_dummy_3[31..0]
#define CONN_HOST_CSR_TOP_BGF_CSR_DUMMY_CR_3_conn_bgf_host_csr_dummy_3_SHFT 0

/* =====================================================================================

  ---WF_CSR_DUMMY_CR_0 (0x18060000 + 0x0190)---

    conn_wf_host_csr_dummy_0[31..0] - (RW) reserved cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_0_conn_wf_host_csr_dummy_0_ADDR CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_0_ADDR
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_0_conn_wf_host_csr_dummy_0_MASK 0xFFFFFFFF                // conn_wf_host_csr_dummy_0[31..0]
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_0_conn_wf_host_csr_dummy_0_SHFT 0

/* =====================================================================================

  ---WF_CSR_DUMMY_CR_1 (0x18060000 + 0x0194)---

    conn_wf_host_csr_dummy_1[31..0] - (RW) reserved cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_1_conn_wf_host_csr_dummy_1_ADDR CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_1_ADDR
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_1_conn_wf_host_csr_dummy_1_MASK 0xFFFFFFFF                // conn_wf_host_csr_dummy_1[31..0]
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_1_conn_wf_host_csr_dummy_1_SHFT 0

/* =====================================================================================

  ---WF_CSR_DUMMY_CR_2 (0x18060000 + 0x0198)---

    conn_wf_host_csr_dummy_2[31..0] - (RW) reserved cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_2_conn_wf_host_csr_dummy_2_ADDR CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_2_ADDR
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_2_conn_wf_host_csr_dummy_2_MASK 0xFFFFFFFF                // conn_wf_host_csr_dummy_2[31..0]
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_2_conn_wf_host_csr_dummy_2_SHFT 0

/* =====================================================================================

  ---WF_CSR_DUMMY_CR_3 (0x18060000 + 0x019c)---

    conn_wf_host_csr_dummy_3[31..0] - (RW) reserved cr

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_3_conn_wf_host_csr_dummy_3_ADDR CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_3_ADDR
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_3_conn_wf_host_csr_dummy_3_MASK 0xFFFFFFFF                // conn_wf_host_csr_dummy_3[31..0]
#define CONN_HOST_CSR_TOP_WF_CSR_DUMMY_CR_3_conn_wf_host_csr_dummy_3_SHFT 0

/* =====================================================================================

  ---DUMMY_RD_DBG (0x18060000 + 0x0200)---

    DUMMY_READ[31..0]            - (RO) It was read only dbg_cr. It alwasys return 0x87654321

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_DUMMY_RD_DBG_DUMMY_READ_ADDR         CONN_HOST_CSR_TOP_DUMMY_RD_DBG_ADDR
#define CONN_HOST_CSR_TOP_DUMMY_RD_DBG_DUMMY_READ_MASK         0xFFFFFFFF                // DUMMY_READ[31..0]
#define CONN_HOST_CSR_TOP_DUMMY_RD_DBG_DUMMY_READ_SHFT         0

/* =====================================================================================

  ---WM_MCU_PC_DBG (0x18060000 + 0x0204)---

    conn_wf_wm_mcu_dbg_pc_log[31..0] - (RO) Mcusys wm_dbg_pc_log.

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WM_MCU_PC_DBG_conn_wf_wm_mcu_dbg_pc_log_ADDR CONN_HOST_CSR_TOP_WM_MCU_PC_DBG_ADDR
#define CONN_HOST_CSR_TOP_WM_MCU_PC_DBG_conn_wf_wm_mcu_dbg_pc_log_MASK 0xFFFFFFFF                // conn_wf_wm_mcu_dbg_pc_log[31..0]
#define CONN_HOST_CSR_TOP_WM_MCU_PC_DBG_conn_wf_wm_mcu_dbg_pc_log_SHFT 0

/* =====================================================================================

  ---WM_MCU_GPR_DBG (0x18060000 + 0x0208)---

    conn_wf_wm_mcu_dbg_gpr_log[31..0] - (RO) Mcusys wm_dbg_gpr_log.

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WM_MCU_GPR_DBG_conn_wf_wm_mcu_dbg_gpr_log_ADDR CONN_HOST_CSR_TOP_WM_MCU_GPR_DBG_ADDR
#define CONN_HOST_CSR_TOP_WM_MCU_GPR_DBG_conn_wf_wm_mcu_dbg_gpr_log_MASK 0xFFFFFFFF                // conn_wf_wm_mcu_dbg_gpr_log[31..0]
#define CONN_HOST_CSR_TOP_WM_MCU_GPR_DBG_conn_wf_wm_mcu_dbg_gpr_log_SHFT 0

/* =====================================================================================

  ---WA_MCU_PC_DBG (0x18060000 + 0x020c)---

    conn_wf_wa_mcu_dbg_pc_log[31..0] - (RO) Mcusys wa_dbg_pc_log.

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WA_MCU_PC_DBG_conn_wf_wa_mcu_dbg_pc_log_ADDR CONN_HOST_CSR_TOP_WA_MCU_PC_DBG_ADDR
#define CONN_HOST_CSR_TOP_WA_MCU_PC_DBG_conn_wf_wa_mcu_dbg_pc_log_MASK 0xFFFFFFFF                // conn_wf_wa_mcu_dbg_pc_log[31..0]
#define CONN_HOST_CSR_TOP_WA_MCU_PC_DBG_conn_wf_wa_mcu_dbg_pc_log_SHFT 0

/* =====================================================================================

  ---WA_MCU_GPR_DBG (0x18060000 + 0x0210)---

    conn_wf_wa_mcu_dbg_gpr_log[31..0] - (RO) Mcusys wa_dbg_gpr_log.

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WA_MCU_GPR_DBG_conn_wf_wa_mcu_dbg_gpr_log_ADDR CONN_HOST_CSR_TOP_WA_MCU_GPR_DBG_ADDR
#define CONN_HOST_CSR_TOP_WA_MCU_GPR_DBG_conn_wf_wa_mcu_dbg_gpr_log_MASK 0xFFFFFFFF                // conn_wf_wa_mcu_dbg_gpr_log[31..0]
#define CONN_HOST_CSR_TOP_WA_MCU_GPR_DBG_conn_wf_wa_mcu_dbg_gpr_log_SHFT 0

/* =====================================================================================

  ---WF_DSLP_DEBUG_PORT (0x18060000 + 0x0214)---

    top_pwr_ack[0]               - (RO) [WF_RGU_DBG]
                                     conn_top_off MTCMOS primary power ack status
                                     0: power-off
                                     1: power-on
    ao_top_pwr_ack_s[1]          - (RO) [WF_RGU_DBG]
                                     conn_top_off MTCMOS secondary power ack status
                                     0: power-off
                                     1: power-on
    p_rgu_top_hw_rst_b[2]        - (RO) [WF_RGU_DBG]
                                     conn_top_off reset status
                                     0: reset
                                     1: not reset
    p_rgu_top_iso_en[3]          - (RO) [WF_RGU_DBG]
                                     conn_top_off output signals isolation status
                                     0: not isolation
                                     1: isolation
    RESERVED4[4]                 - (RO) Reserved bits
    p_rgu_top_pwr_on[5]          - (RO) [WF_RGU_DBG]
                                     conn_top_off MTCMOS primary power status
                                     0: power-off
                                     1: power-on
    top_cfg_dslp_req[6]          - (RO) [WF_RGU_DBG]
                                     conn_top_off MTCMOS power control
                                     0: power-on request
                                     1: power-off request
    rgu_top_dslp_ack[7]          - (RO) [WF_RGU_DBG]
                                     conn_top_off MTCMOS power control status
                                     0: power-off
                                     1: power-on
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_rgu_top_dslp_ack_ADDR CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ADDR
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_rgu_top_dslp_ack_MASK 0x00000080                // rgu_top_dslp_ack[7]
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_rgu_top_dslp_ack_SHFT 7
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_top_cfg_dslp_req_ADDR CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ADDR
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_top_cfg_dslp_req_MASK 0x00000040                // top_cfg_dslp_req[6]
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_top_cfg_dslp_req_SHFT 6
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_p_rgu_top_pwr_on_ADDR CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ADDR
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_p_rgu_top_pwr_on_MASK 0x00000020                // p_rgu_top_pwr_on[5]
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_p_rgu_top_pwr_on_SHFT 5
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_p_rgu_top_iso_en_ADDR CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ADDR
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_p_rgu_top_iso_en_MASK 0x00000008                // p_rgu_top_iso_en[3]
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_p_rgu_top_iso_en_SHFT 3
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_p_rgu_top_hw_rst_b_ADDR CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ADDR
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_p_rgu_top_hw_rst_b_MASK 0x00000004                // p_rgu_top_hw_rst_b[2]
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_p_rgu_top_hw_rst_b_SHFT 2
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ao_top_pwr_ack_s_ADDR CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ADDR
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ao_top_pwr_ack_s_MASK 0x00000002                // ao_top_pwr_ack_s[1]
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ao_top_pwr_ack_s_SHFT 1
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_top_pwr_ack_ADDR  CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_ADDR
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_top_pwr_ack_MASK  0x00000001                // top_pwr_ack[0]
#define CONN_HOST_CSR_TOP_WF_DSLP_DEBUG_PORT_top_pwr_ack_SHFT  0

/* =====================================================================================

  ---MCU_WF_ON_DBG (0x18060000 + 0x0218)---

    sif_ahb_on[0]                - (RO) [WFSYS_ON_DBG]
                                     LMAC APB Bus active status.
    sw_on_state_event[1]         - (RO) [WFSYS_ON_DBG]
                                     LP ownership back temp status ,
                                     1. When FW set OWN , this signal will keep high until LP ownership back to FW.
                                     2. Interrupt occurred, this signal will keep high until FW clear interrupt & FW set LP ownership back to FW done.
    wifi_mac_irq_b[2]            - (RO) [WFSYS_ON_DBG]
                                     LMAC interrupt status :
                                     0 : Interrupt occurred
                                     1 : no interrupt
    wf_off_ckt_rdy[3]            - (RO) [WFSYS_ON_DBG]
                                     WiFi mtcmos power on indicator
    wfsys_on_sleep_fsm[7..4]     - (RO) [WFSYS_ON_DBG]
                                     WiFi sleep_wakeup state machine :
                                     0x0 : IDLE
                                     0x1 : FETCH
                                     0x2 : INITIAL
                                     0x3 : PRE_BU
                                     0x4 : WLAN_ON
                                     0x5 : SLEEP
                                     0x6 : POST_RS
                                     0x7 : CLK_ON 
                                     0x8 : CLK_OFF
    conn_ap_bus_req[8]           - (RO) [MCUSYS_N9_DBG]
                                     Request ap bus usage to SPM
    conn2ap_emi_req[9]           - (RO) [MCUSYS_N9_DBG]
                                     Conn2ap apsrc request for enable EMI MTCMOS and PLL
    ap2conn_emi_ack[10]          - (RO) [MCUSYS_N9_DBG]
                                     Conn2ap apsrc acknowledge for enable EMI MTCMOS and PLL
    conn_ddr_en[11]              - (RO) [MCUSYS_N9_DBG]
                                     Conn2ap ddr request to SPM for enable EMI
    conn2ap_sw_irq_b[12]         - (RO) [MCUSYS_N9_DBG]
                                     SW trigger interrupt to AP side in mcu_confg.EMI_CTL
    pdn_mcu[13]                  - (RO) [MCUSYS_N9_DBG]
                                     0: n9 active
                                     1: n9 standby & clock gated
    standby[14]                  - (RO) [MCUSYS_N9_DBG]
                                     N9 enter standby mode(legacy sleep)
                                     0: n9 active
                                     1: n9 standby
    ahb_ck_en[15]                - (RO) [MCUSYS_N9_DBG]
                                     AHB bus clock gating
    fiq_b[16]                    - (RO) [CIRQ_DBG_PORT]
                                     Fast interrupt request from cirq to n9, active low
                                     0: interrupt active
                                     1: no fiq interrupt
    irq_b[17]                    - (RO) [CIRQ_DBG_PORT]
                                     Interrupt from cirq to n9, active low
                                     0: interrupt active
                                     1: no irq interrupt
    eint_event_b[18]             - (RO) [CIRQ_DBG_PORT]
                                     Eint enter cirq to wakeup mcusys deep sleep, active low
                                     0: eint active
                                     1: no eint event
    cirq_int_n[19]               - (RO) [CIRQ_DBG_PORT]
                                     Means irq or eint enter cirq to wakeup mcusys legacy sleep, active low
                                     0: interrupt active
                                     1: no interrupt
    eint_32k_s2[20]              - (RO) [CIRQ_DBG_PORT]
                                     Sync from ~eint_event_b, active high
                                     0: no eint active
                                     1: eint active
    cirq_int_n_sync[21]          - (RO) [CIRQ_DBG_PORT]
                                     Sync from cirq_int_n, active low
                                     0: interrupt active
                                     1: no interrupt
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_cirq_int_n_sync_ADDR   CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_cirq_int_n_sync_MASK   0x00200000                // cirq_int_n_sync[21]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_cirq_int_n_sync_SHFT   21
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_eint_32k_s2_ADDR       CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_eint_32k_s2_MASK       0x00100000                // eint_32k_s2[20]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_eint_32k_s2_SHFT       20
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_cirq_int_n_ADDR        CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_cirq_int_n_MASK        0x00080000                // cirq_int_n[19]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_cirq_int_n_SHFT        19
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_eint_event_b_ADDR      CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_eint_event_b_MASK      0x00040000                // eint_event_b[18]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_eint_event_b_SHFT      18
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_irq_b_ADDR             CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_irq_b_MASK             0x00020000                // irq_b[17]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_irq_b_SHFT             17
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_fiq_b_ADDR             CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_fiq_b_MASK             0x00010000                // fiq_b[16]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_fiq_b_SHFT             16
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ahb_ck_en_ADDR         CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ahb_ck_en_MASK         0x00008000                // ahb_ck_en[15]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ahb_ck_en_SHFT         15
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_standby_ADDR           CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_standby_MASK           0x00004000                // standby[14]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_standby_SHFT           14
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_pdn_mcu_ADDR           CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_pdn_mcu_MASK           0x00002000                // pdn_mcu[13]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_pdn_mcu_SHFT           13
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn2ap_sw_irq_b_ADDR  CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn2ap_sw_irq_b_MASK  0x00001000                // conn2ap_sw_irq_b[12]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn2ap_sw_irq_b_SHFT  12
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn_ddr_en_ADDR       CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn_ddr_en_MASK       0x00000800                // conn_ddr_en[11]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn_ddr_en_SHFT       11
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ap2conn_emi_ack_ADDR   CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ap2conn_emi_ack_MASK   0x00000400                // ap2conn_emi_ack[10]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ap2conn_emi_ack_SHFT   10
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn2ap_emi_req_ADDR   CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn2ap_emi_req_MASK   0x00000200                // conn2ap_emi_req[9]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn2ap_emi_req_SHFT   9
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn_ap_bus_req_ADDR   CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn_ap_bus_req_MASK   0x00000100                // conn_ap_bus_req[8]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_conn_ap_bus_req_SHFT   8
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_wfsys_on_sleep_fsm_ADDR CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_wfsys_on_sleep_fsm_MASK 0x000000F0                // wfsys_on_sleep_fsm[7..4]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_wfsys_on_sleep_fsm_SHFT 4
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_wf_off_ckt_rdy_ADDR    CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_wf_off_ckt_rdy_MASK    0x00000008                // wf_off_ckt_rdy[3]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_wf_off_ckt_rdy_SHFT    3
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_wifi_mac_irq_b_ADDR    CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_wifi_mac_irq_b_MASK    0x00000004                // wifi_mac_irq_b[2]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_wifi_mac_irq_b_SHFT    2
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_sw_on_state_event_ADDR CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_sw_on_state_event_MASK 0x00000002                // sw_on_state_event[1]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_sw_on_state_event_SHFT 1
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_sif_ahb_on_ADDR        CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_sif_ahb_on_MASK        0x00000001                // sif_ahb_on[0]
#define CONN_HOST_CSR_TOP_MCU_WF_ON_DBG_sif_ahb_on_SHFT        0

/* =====================================================================================

  ---WFSYS_MONFLG_OUT (0x18060000 + 0x021c)---

    conn_wf_aon_dbg_flag[31..0]  - (RO) [CONN_AON_MON_FLAG]
                                     conn_aon_dbg_flag. It can select by conn_monflag_on.
                                     conn_monflag debug setting should reference to monflag programming guide.

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WFSYS_MONFLG_OUT_conn_wf_aon_dbg_flag_ADDR CONN_HOST_CSR_TOP_WFSYS_MONFLG_OUT_ADDR
#define CONN_HOST_CSR_TOP_WFSYS_MONFLG_OUT_conn_wf_aon_dbg_flag_MASK 0xFFFFFFFF                // conn_wf_aon_dbg_flag[31..0]
#define CONN_HOST_CSR_TOP_WFSYS_MONFLG_OUT_conn_wf_aon_dbg_flag_SHFT 0

/* =====================================================================================

  ---WF_MET_CFG_ON_EVENT_DATA (0x18060000 + 0x0220)---

    hw_control[0]                - (RO) [CONN_CFG_ON_DBG]
                                     HW control mode, if set 1, then 
                                     1)  connsys stays in standby state if MCU still works
                                     2) connsys stays in idle state if there is only osc request and MCU sleeps
                                     3) connsys stays in dsleep state if no osc request or no interrupt
    mcu_pwr_stat[3..1]           - (RO) [CONN_CFG_ON_DBG]
                                     MCU power state
                                     3'b001 : standby state (mcu active)
                                     3'b010 : idle state
                                     3'b100 : dsleep state
    mcu_stop[4]                  - (RO) [CONN_CFG_ON_DBG]
                                     MCU stop signal from MCU, which is a necessary condition for dsleep mode
    top_dsleep[5]                - (RO) [CONN_CFG_ON_DBG]
                                     dsleep signal for RGU to rurn on/off MCU power domain
                                     0 : turn on MCU power domain
                                     1 : turn off MCU power domain
    conn_mcu_mdm_pdn[6]          - (RO) not used now
    rgu_mcu_mem_rst_b[7]         - (RO) [CONN_CFG_ON_DBG]
                                     MCU memory reset from RGU
    eint_lv[8]                   - (RO) [CONN_CFG_ON_DBG]
                                     EINT level latched by sleep controller
                                     1) if hw_control = 0, then eint_lv = 0
                                     2) if hw_control = 1, then eint_lv = 1 if MCU sends EINT to sleep controller
    cmdbt_busy[9]                - (RO) [CONN_CFG_ON_DBG]
                                     Indicator of CMDBT busy state, if 1, then backup/restore is in process
    cmdbt_use_pll[10]            - (RO) [CONN_CFG_ON_DBG]
                                     Indicator of using PLL clock for WiFi backup and restore
    cpu_clk_en[11]               - (RO) [CONN_CFG_ON_DBG]
                                     CPU clock enable signal
                                     1) if hw_control = 0, then cpu_clk_en = 1
                                     2) if hw_control = 1, then cpu_clk_en is con-trolled by sleep controller
                                     3) cpu_clk_en = 0 in dsleep and idle state
    bus_clk_en[12]               - (RO) [CONN_CFG_ON_DBG]
                                     MCU bus clock enable signal
                                     1) if hw_control = 0, then bus_clk_en = 1
                                     2) if hw_control = 1, then bus_clk_en is con-trolled by sleep controller
                                     3) bus_clk_en = 0 in dsleep state
    osc_rdy[13]                  - (RO) [CONN_CFG_ON_DBG]
                                     OSC switch ready signals, if 1, then it means
                                     1) host OSC clock source is ready
                                     2) connsys internal OSC counter is counted to target count
                                     3) could be set 1 by CR (cr_force_osc_rdy)
    hwctrl_osc_en[14]            - (RO) [CONN_CFG_ON_DBG]
                                     OSC control signal to activate OSC control FSM, conditions are as below:
                                     1) IP needs osc clock (~hw_control | osc_en)
                                     2) external interrupt (EINT)
                                     3) 32k not ready. cannot turn off
                                     4) CR set (cr_xo_no_off)
                                     5) CR set for FM (cr_fm_xo_on)
    osc_en_all[15]               - (RO) [CONN_CFG_ON_DBG]
                                     OSC request signal from IP/hif/host to wake up connsys or at least stay in idle state
                                     0: no osc request
                                     1: at least one or more osc requests
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_osc_en_all_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_osc_en_all_MASK 0x00008000                // osc_en_all[15]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_osc_en_all_SHFT 15
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_hwctrl_osc_en_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_hwctrl_osc_en_MASK 0x00004000                // hwctrl_osc_en[14]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_hwctrl_osc_en_SHFT 14
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_osc_rdy_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_osc_rdy_MASK 0x00002000                // osc_rdy[13]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_osc_rdy_SHFT 13
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_bus_clk_en_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_bus_clk_en_MASK 0x00001000                // bus_clk_en[12]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_bus_clk_en_SHFT 12
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_cpu_clk_en_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_cpu_clk_en_MASK 0x00000800                // cpu_clk_en[11]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_cpu_clk_en_SHFT 11
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_cmdbt_use_pll_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_cmdbt_use_pll_MASK 0x00000400                // cmdbt_use_pll[10]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_cmdbt_use_pll_SHFT 10
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_cmdbt_busy_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_cmdbt_busy_MASK 0x00000200                // cmdbt_busy[9]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_cmdbt_busy_SHFT 9
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_eint_lv_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_eint_lv_MASK 0x00000100                // eint_lv[8]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_eint_lv_SHFT 8
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_rgu_mcu_mem_rst_b_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_rgu_mcu_mem_rst_b_MASK 0x00000080                // rgu_mcu_mem_rst_b[7]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_rgu_mcu_mem_rst_b_SHFT 7
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_conn_mcu_mdm_pdn_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_conn_mcu_mdm_pdn_MASK 0x00000040                // conn_mcu_mdm_pdn[6]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_conn_mcu_mdm_pdn_SHFT 6
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_top_dsleep_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_top_dsleep_MASK 0x00000020                // top_dsleep[5]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_top_dsleep_SHFT 5
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_mcu_stop_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_mcu_stop_MASK 0x00000010                // mcu_stop[4]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_mcu_stop_SHFT 4
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_mcu_pwr_stat_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_mcu_pwr_stat_MASK 0x0000000E                // mcu_pwr_stat[3..1]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_mcu_pwr_stat_SHFT 1
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_hw_control_ADDR CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_hw_control_MASK 0x00000001                // hw_control[0]
#define CONN_HOST_CSR_TOP_WF_MET_CFG_ON_EVENT_DATA_hw_control_SHFT 0

/* =====================================================================================

  ---BGF_MCU_PC_DBG (0x18060000 + 0x022c)---

    conn_bgf_mcu_dbg_pc_log[31..0] - (RO) Mcusys bgf_dbg_pc_log.

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_DBG_conn_bgf_mcu_dbg_pc_log_ADDR CONN_HOST_CSR_TOP_BGF_MCU_PC_DBG_ADDR
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_DBG_conn_bgf_mcu_dbg_pc_log_MASK 0xFFFFFFFF                // conn_bgf_mcu_dbg_pc_log[31..0]
#define CONN_HOST_CSR_TOP_BGF_MCU_PC_DBG_conn_bgf_mcu_dbg_pc_log_SHFT 0

/* =====================================================================================

  ---BGF_DSLP_DBG (0x18060000 + 0x0230)---

    top_pwr_ack[0]               - (RO) [BGF_RGU_DBG]
                                     conn_top_off MTCMOS primary power ack status
                                     0: power-off
                                     1: power-on
    ao_top_pwr_ack_s[1]          - (RO) [BGF_RGU_DBG]
                                     conn_top_off MTCMOS secondary power ack status
                                     0: power-off
                                     1: power-on
    p_rgu_top_hw_rst_b[2]        - (RO) [BGF_RGU_DBG]
                                     conn_top_off reset status
                                     0: reset
                                     1: not reset
    p_rgu_top_iso_en[3]          - (RO) [BGF_RGU_DBG]
                                     conn_top_off output signals isolation status
                                     0: not isolation
                                     1: isolation
    RESERVED4[4]                 - (RO) Reserved bits
    p_rgu_top_pwr_on[5]          - (RO) [BGF_RGU_DBG]
                                     conn_top_off MTCMOS primary power status
                                     0: power-off
                                     1: power-on
    top_cfg_dslp_req[6]          - (RO) [BGF_RGU_DBG]
                                     conn_top_off MTCMOS power control
                                     0: power-on request
                                     1: power-off request
    rgu_top_dslp_ack[7]          - (RO) [BGF_RGU_DBG]
                                     conn_top_off MTCMOS power control status
                                     0: power-off
                                     1: power-on
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_rgu_top_dslp_ack_ADDR   CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ADDR
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_rgu_top_dslp_ack_MASK   0x00000080                // rgu_top_dslp_ack[7]
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_rgu_top_dslp_ack_SHFT   7
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_top_cfg_dslp_req_ADDR   CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ADDR
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_top_cfg_dslp_req_MASK   0x00000040                // top_cfg_dslp_req[6]
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_top_cfg_dslp_req_SHFT   6
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_p_rgu_top_pwr_on_ADDR   CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ADDR
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_p_rgu_top_pwr_on_MASK   0x00000020                // p_rgu_top_pwr_on[5]
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_p_rgu_top_pwr_on_SHFT   5
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_p_rgu_top_iso_en_ADDR   CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ADDR
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_p_rgu_top_iso_en_MASK   0x00000008                // p_rgu_top_iso_en[3]
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_p_rgu_top_iso_en_SHFT   3
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_p_rgu_top_hw_rst_b_ADDR CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ADDR
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_p_rgu_top_hw_rst_b_MASK 0x00000004                // p_rgu_top_hw_rst_b[2]
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_p_rgu_top_hw_rst_b_SHFT 2
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ao_top_pwr_ack_s_ADDR   CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ADDR
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ao_top_pwr_ack_s_MASK   0x00000002                // ao_top_pwr_ack_s[1]
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ao_top_pwr_ack_s_SHFT   1
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_top_pwr_ack_ADDR        CONN_HOST_CSR_TOP_BGF_DSLP_DBG_ADDR
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_top_pwr_ack_MASK        0x00000001                // top_pwr_ack[0]
#define CONN_HOST_CSR_TOP_BGF_DSLP_DBG_top_pwr_ack_SHFT        0

/* =====================================================================================

  ---MCU_BGF_ON_DBG (0x18060000 + 0x0234)---

    RESERVED0[7..0]              - (RO) Reserved bits
    conn_ap_bus_req[8]           - (RO) [MCUSYS_N9_DBG]
                                     Request ap bus usage to SPM
    conn2ap_emi_req[9]           - (RO) [MCUSYS_N9_DBG]
                                     Conn2ap apsrc request for enable EMI MTCMOS and PLL
    ap2conn_emi_ack[10]          - (RO) [MCUSYS_N9_DBG]
                                     Conn2ap apsrc acknowledge for enable EMI MTCMOS and PLL
    conn_ddr_en[11]              - (RO) [MCUSYS_N9_DBG]
                                     Conn2ap ddr request to SPM for enable EMI
    conn2ap_sw_irq_b[12]         - (RO) [MCUSYS_N9_DBG]
                                     SW trigger interrupt to AP side in mcu_confg.EMI_CTL
    pdn_mcu[13]                  - (RO) [MCUSYS_N9_DBG]
                                     0: n9 active
                                     1: n9 standby & clock gated
    standby[14]                  - (RO) [MCUSYS_N9_DBG]
                                     N9 enter standby mode(legacy sleep)
                                     0: n9 active
                                     1: n9 standby
    ahb_ck_en[15]                - (RO) [MCUSYS_N9_DBG]
                                     AHB bus clock gating
    fiq_b[16]                    - (RO) [CIRQ_DBG_PORT]
                                     Fast interrupt request from cirq to n9, active low
                                     0: interrupt active
                                     1: no fiq interrupt
    irq_b[17]                    - (RO) [CIRQ_DBG_PORT]
                                     Interrupt from cirq to n9, active low
                                     0: interrupt active
                                     1: no irq interrupt
    eint_event_b[18]             - (RO) [CIRQ_DBG_PORT]
                                     Eint enter cirq to wakeup mcusys deep sleep, active low
                                     0: eint active
                                     1: no eint event
    cirq_int_n[19]               - (RO) [CIRQ_DBG_PORT]
                                     Means irq or eint enter cirq to wakeup mcusys legacy sleep, active low
                                     0: interrupt active
                                     1: no interrupt
    eint_32k_s2[20]              - (RO) [CIRQ_DBG_PORT]
                                     Sync from ~eint_event_b, active high
                                     0: no eint active
                                     1: eint active
    cirq_int_n_sync[21]          - (RO) [CIRQ_DBG_PORT]
                                     Sync from ~eint_event_b, active high
                                     0: no eint active
                                     1: eint active
    dbg_nim_irq[22]              - (RO) [CIRQ_DBG_PORT]
                                     Sync from cirq_int_n, active low
                                     0: interrupt active
                                     1: no interrupt
    RESERVED23[31..23]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_dbg_nim_irq_ADDR      CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_dbg_nim_irq_MASK      0x00400000                // dbg_nim_irq[22]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_dbg_nim_irq_SHFT      22
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_cirq_int_n_sync_ADDR  CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_cirq_int_n_sync_MASK  0x00200000                // cirq_int_n_sync[21]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_cirq_int_n_sync_SHFT  21
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_eint_32k_s2_ADDR      CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_eint_32k_s2_MASK      0x00100000                // eint_32k_s2[20]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_eint_32k_s2_SHFT      20
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_cirq_int_n_ADDR       CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_cirq_int_n_MASK       0x00080000                // cirq_int_n[19]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_cirq_int_n_SHFT       19
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_eint_event_b_ADDR     CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_eint_event_b_MASK     0x00040000                // eint_event_b[18]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_eint_event_b_SHFT     18
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_irq_b_ADDR            CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_irq_b_MASK            0x00020000                // irq_b[17]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_irq_b_SHFT            17
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_fiq_b_ADDR            CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_fiq_b_MASK            0x00010000                // fiq_b[16]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_fiq_b_SHFT            16
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ahb_ck_en_ADDR        CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ahb_ck_en_MASK        0x00008000                // ahb_ck_en[15]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ahb_ck_en_SHFT        15
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_standby_ADDR          CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_standby_MASK          0x00004000                // standby[14]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_standby_SHFT          14
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_pdn_mcu_ADDR          CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_pdn_mcu_MASK          0x00002000                // pdn_mcu[13]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_pdn_mcu_SHFT          13
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn2ap_sw_irq_b_ADDR CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn2ap_sw_irq_b_MASK 0x00001000                // conn2ap_sw_irq_b[12]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn2ap_sw_irq_b_SHFT 12
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn_ddr_en_ADDR      CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn_ddr_en_MASK      0x00000800                // conn_ddr_en[11]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn_ddr_en_SHFT      11
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ap2conn_emi_ack_ADDR  CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ap2conn_emi_ack_MASK  0x00000400                // ap2conn_emi_ack[10]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ap2conn_emi_ack_SHFT  10
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn2ap_emi_req_ADDR  CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn2ap_emi_req_MASK  0x00000200                // conn2ap_emi_req[9]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn2ap_emi_req_SHFT  9
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn_ap_bus_req_ADDR  CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn_ap_bus_req_MASK  0x00000100                // conn_ap_bus_req[8]
#define CONN_HOST_CSR_TOP_MCU_BGF_ON_DBG_conn_ap_bus_req_SHFT  8

/* =====================================================================================

  ---BGFSYS_MONFLG_OUT (0x18060000 + 0x0238)---

    conn_bgf_aon_dbg_flag[31..0] - (RO) [CONN_AON_MON_FLAG]
                                     conn_aon_dbg_flag. It can select by conn_monflag_on.
                                     conn_monflag debug setting should reference to monflag programming guide.

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGFSYS_MONFLG_OUT_conn_bgf_aon_dbg_flag_ADDR CONN_HOST_CSR_TOP_BGFSYS_MONFLG_OUT_ADDR
#define CONN_HOST_CSR_TOP_BGFSYS_MONFLG_OUT_conn_bgf_aon_dbg_flag_MASK 0xFFFFFFFF                // conn_bgf_aon_dbg_flag[31..0]
#define CONN_HOST_CSR_TOP_BGFSYS_MONFLG_OUT_conn_bgf_aon_dbg_flag_SHFT 0

/* =====================================================================================

  ---BGF_MET_CFG_ON_EVENT_DATA (0x18060000 + 0x023c)---

    RESERVED0[15..0]             - (RO) Reserved bits
    hw_control[16]               - (RO) [BGF_CFG_ON_DBG]
                                     HW control mode, if set 1, then 
                                     1)  connsys stays in standby state if MCU still works
                                     2) connsys stays in idle state if there is only osc request and MCU sleeps
                                     3) connsys stays in dsleep state if no osc request or no interrupt
    mcu_pwr_stat[19..17]         - (RO) [BGF_CFG_ON_DBG]
                                     MCU power state
                                     3'b001 : standby state (mcu active)
                                     3'b010 : idle state
                                     3'b100 : dsleep state
    mcu_stop[20]                 - (RO) [BGF_CFG_ON_DBG]
                                     MCU stop signal from MCU, which is a necessary condition for dsleep mode
    top_dsleep[21]               - (RO) [BGF_CFG_ON_DBG]
                                     dsleep signal for RGU to rurn on/off MCU power domain
                                     0 : turn on MCU power domain
                                     1 : turn off MCU power domain
    conn_mcu_mdm_pdn[22]         - (RO) not used now
    rgu_mcu_mem_rst_b[23]        - (RO) [BGF_CFG_ON_DBG]
                                     MCU memory reset from RGU
    eint_lv[24]                  - (RO) [BGF_CFG_ON_DBG]
                                     EINT level latched by sleep controller
                                     1) if hw_control = 0, then eint_lv = 0
                                     2) if hw_control = 1, then eint_lv = 1 if MCU sends EINT to sleep controller
    cmdbt_busy[25]               - (RO) [BGF_CFG_ON_DBG]
                                     Indicator of CMDBT busy state, if 1, then backup/restore is in process
    cmdbt_use_pll[26]            - (RO) [BGF_CFG_ON_DBG]
                                     Indicator of using PLL clock for WiFi backup and restore
    cpu_clk_en[27]               - (RO) [BGF_CFG_ON_DBG]
                                     CPU clock enable signal
                                     1) if hw_control = 0, then cpu_clk_en = 1
                                     2) if hw_control = 1, then cpu_clk_en is con-trolled by sleep controller
                                     3) cpu_clk_en = 0 in dsleep and idle state
    bus_clk_en[28]               - (RO) [BGF_CFG_ON_DBG]
                                     MCU bus clock enable signal
                                     1) if hw_control = 0, then bus_clk_en = 1
                                     2) if hw_control = 1, then bus_clk_en is con-trolled by sleep controller
                                     3) bus_clk_en = 0 in dsleep state
    osc_rdy[29]                  - (RO) [BGF_CFG_ON_DBG]
                                     OSC switch ready signals, if 1, then it means
                                     1) host OSC clock source is ready
                                     2) connsys internal OSC counter is counted to target count
                                     3) could be set 1 by CR (cr_force_osc_rdy)
    hwctrl_osc_en[30]            - (RO) [BGF_CFG_ON_DBG]
                                     OSC control signal to activate OSC control FSM, conditions are as below:
                                     1) IP needs osc clock (~hw_control | osc_en)
                                     2) external interrupt (EINT)
                                     3) 32k not ready. cannot turn off
                                     4) CR set (cr_xo_no_off)
                                     5) CR set for FM (cr_fm_xo_on)
    osc_en_all[31]               - (RO) [BGF_CFG_ON_DBG]
                                     OSC request signal from IP/hif/host to wake up connsys or at least stay in idle state
                                     0: no osc request
                                     1: at least one or more osc requests

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_osc_en_all_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_osc_en_all_MASK 0x80000000                // osc_en_all[31]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_osc_en_all_SHFT 31
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_hwctrl_osc_en_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_hwctrl_osc_en_MASK 0x40000000                // hwctrl_osc_en[30]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_hwctrl_osc_en_SHFT 30
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_osc_rdy_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_osc_rdy_MASK 0x20000000                // osc_rdy[29]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_osc_rdy_SHFT 29
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_bus_clk_en_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_bus_clk_en_MASK 0x10000000                // bus_clk_en[28]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_bus_clk_en_SHFT 28
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_cpu_clk_en_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_cpu_clk_en_MASK 0x08000000                // cpu_clk_en[27]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_cpu_clk_en_SHFT 27
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_cmdbt_use_pll_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_cmdbt_use_pll_MASK 0x04000000                // cmdbt_use_pll[26]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_cmdbt_use_pll_SHFT 26
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_cmdbt_busy_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_cmdbt_busy_MASK 0x02000000                // cmdbt_busy[25]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_cmdbt_busy_SHFT 25
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_eint_lv_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_eint_lv_MASK 0x01000000                // eint_lv[24]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_eint_lv_SHFT 24
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_rgu_mcu_mem_rst_b_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_rgu_mcu_mem_rst_b_MASK 0x00800000                // rgu_mcu_mem_rst_b[23]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_rgu_mcu_mem_rst_b_SHFT 23
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_conn_mcu_mdm_pdn_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_conn_mcu_mdm_pdn_MASK 0x00400000                // conn_mcu_mdm_pdn[22]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_conn_mcu_mdm_pdn_SHFT 22
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_top_dsleep_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_top_dsleep_MASK 0x00200000                // top_dsleep[21]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_top_dsleep_SHFT 21
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_mcu_stop_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_mcu_stop_MASK 0x00100000                // mcu_stop[20]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_mcu_stop_SHFT 20
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_mcu_pwr_stat_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_mcu_pwr_stat_MASK 0x000E0000                // mcu_pwr_stat[19..17]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_mcu_pwr_stat_SHFT 17
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_hw_control_ADDR CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_ADDR
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_hw_control_MASK 0x00010000                // hw_control[16]
#define CONN_HOST_CSR_TOP_BGF_MET_CFG_ON_EVENT_DATA_hw_control_SHFT 16

/* =====================================================================================

  ---WF_MAILBOX_DBG (0x18060000 + 0x0260)---

    host_mailbox_wf[31..0]       - (RO) [SW_MAILBOX]
                                     HOST read mail_box information when mcu in deep sleep. The mailbox value can be configure in conn_mcu_cfg_on [0x81030100] HOST_MAILBOX_WF

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_WF_MAILBOX_DBG_host_mailbox_wf_ADDR  CONN_HOST_CSR_TOP_WF_MAILBOX_DBG_ADDR
#define CONN_HOST_CSR_TOP_WF_MAILBOX_DBG_host_mailbox_wf_MASK  0xFFFFFFFF                // host_mailbox_wf[31..0]
#define CONN_HOST_CSR_TOP_WF_MAILBOX_DBG_host_mailbox_wf_SHFT  0

/* =====================================================================================

  ---N13_MCU_MAILBOX_DBG (0x18060000 + 0x0264)---

    host_mailbox_n13_mcu[31..0]  - (RO) [SW_MAILBOX]
                                     HOST read mail_box information when mcu in deep sleep. The mailbox value can be configure in conn_mcu_cfg_on [0x81030104] HOST_MAILBOX_MCU_N13

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_N13_MCU_MAILBOX_DBG_host_mailbox_n13_mcu_ADDR CONN_HOST_CSR_TOP_N13_MCU_MAILBOX_DBG_ADDR
#define CONN_HOST_CSR_TOP_N13_MCU_MAILBOX_DBG_host_mailbox_n13_mcu_MASK 0xFFFFFFFF                // host_mailbox_n13_mcu[31..0]
#define CONN_HOST_CSR_TOP_N13_MCU_MAILBOX_DBG_host_mailbox_n13_mcu_SHFT 0

/* =====================================================================================

  ---N9_MCU_MAILBOX_DBG (0x18060000 + 0x0268)---

    host_mailbox_n9_mcu[31..0]   - (RO) [SW_MAILBOX]
                                     HOST read mail_box information when mcu in deep sleep. The mailbox value can be configure in conn_mcu_cfg_on [0x81030104] HOST_MAILBOX_MCU_N9

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_N9_MCU_MAILBOX_DBG_host_mailbox_n9_mcu_ADDR CONN_HOST_CSR_TOP_N9_MCU_MAILBOX_DBG_ADDR
#define CONN_HOST_CSR_TOP_N9_MCU_MAILBOX_DBG_host_mailbox_n9_mcu_MASK 0xFFFFFFFF                // host_mailbox_n9_mcu[31..0]
#define CONN_HOST_CSR_TOP_N9_MCU_MAILBOX_DBG_host_mailbox_n9_mcu_SHFT 0

/* =====================================================================================

  ---BT_MAILBOX_DBG (0x18060000 + 0x026c)---

    host_mailbox_bt[31..0]       - (RO) [SW_MAILBOX]
                                     HOST read mail_box information when mcu in deep sleep. The mailbox value can be configure in conn_mcu_cfg_on [0x81030108] HOST_MAILBOX_BT

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_BT_MAILBOX_DBG_host_mailbox_bt_ADDR  CONN_HOST_CSR_TOP_BT_MAILBOX_DBG_ADDR
#define CONN_HOST_CSR_TOP_BT_MAILBOX_DBG_host_mailbox_bt_MASK  0xFFFFFFFF                // host_mailbox_bt[31..0]
#define CONN_HOST_CSR_TOP_BT_MAILBOX_DBG_host_mailbox_bt_SHFT  0

/* =====================================================================================

  ---GPS_MAILBOX_DBG (0x18060000 + 0x0270)---

    host_mailbox_gps[31..0]      - (RO) [SW_MAILBOX]
                                     HOST read mail_box information when mcu in deep sleep. The mailbox value can be configure in conn_mcu_cfg_on [0x8103010c] HOST_MAILBOX_GPS

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_GPS_MAILBOX_DBG_host_mailbox_gps_ADDR CONN_HOST_CSR_TOP_GPS_MAILBOX_DBG_ADDR
#define CONN_HOST_CSR_TOP_GPS_MAILBOX_DBG_host_mailbox_gps_MASK 0xFFFFFFFF                // host_mailbox_gps[31..0]
#define CONN_HOST_CSR_TOP_GPS_MAILBOX_DBG_host_mailbox_gps_SHFT 0

/* =====================================================================================

  ---MD_MAILBOX_DBG (0x18060000 + 0x0274)---

    host_mailbox_md[31..0]       - (RO) [SW_MAILBOX]
                                     HOST read mail_box information when mcu in deep sleep. The mailbox value can be configure in conn_mcu_cfg_on [0x8103010c] HOST_MAILBOX_GPS

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MD_MAILBOX_DBG_host_mailbox_md_ADDR  CONN_HOST_CSR_TOP_MD_MAILBOX_DBG_ADDR
#define CONN_HOST_CSR_TOP_MD_MAILBOX_DBG_host_mailbox_md_MASK  0xFFFFFFFF                // host_mailbox_md[31..0]
#define CONN_HOST_CSR_TOP_MD_MAILBOX_DBG_host_mailbox_md_SHFT  0

/* =====================================================================================

  ---CONN_HIF_HOST_DEBUG (0x18060000 + 0x0280)---

    conn_hif_host_debug[31..0]   - (RO) [CONN_HIF_HOST_DEBUG]
                                     Internal hw status - conn_infra on domain interface debug signal

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_HIF_HOST_DEBUG_conn_hif_host_debug_ADDR CONN_HOST_CSR_TOP_CONN_HIF_HOST_DEBUG_ADDR
#define CONN_HOST_CSR_TOP_CONN_HIF_HOST_DEBUG_conn_hif_host_debug_MASK 0xFFFFFFFF                // conn_hif_host_debug[31..0]
#define CONN_HOST_CSR_TOP_CONN_HIF_HOST_DEBUG_conn_hif_host_debug_SHFT 0

/* =====================================================================================

  ---CONN_HIF_ON_GLUE_DBG (0x18060000 + 0x0284)---

    conn_hif_on_gule_debug[31..0] - (RO) [CONN_HIF_ON_GULE_DBG]
                                     Internal hw status - fw own & driver own sync signal debug

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_GLUE_DBG_conn_hif_on_gule_debug_ADDR CONN_HOST_CSR_TOP_CONN_HIF_ON_GLUE_DBG_ADDR
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_GLUE_DBG_conn_hif_on_gule_debug_MASK 0xFFFFFFFF                // conn_hif_on_gule_debug[31..0]
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_GLUE_DBG_conn_hif_on_gule_debug_SHFT 0

/* =====================================================================================

  ---CONN_HIF_ON_DBG (0x18060000 + 0x0288)---

    conn_hif_on_debug[31..0]     - (RO) [CONN_HIF_ON_DBG]
                                     Internal hw status - debug selection from glue_dbg or host_dbg or misc_dbg or ap2conn_GALS_SLV_debug

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_DBG_conn_hif_on_debug_ADDR CONN_HOST_CSR_TOP_CONN_HIF_ON_DBG_ADDR
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_DBG_conn_hif_on_debug_MASK 0xFFFFFFFF                // conn_hif_on_debug[31..0]
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_DBG_conn_hif_on_debug_SHFT 0

/* =====================================================================================

  ---CONN_HIF_ON_MISC_DBG (0x18060000 + 0x028c)---

    conn_hif_on_misc_debug[31..0] - (RO) [CONN_HIF_ON_MISC_DBG]
                                     Internal hw status - conn_infra clk detect state & bus idle state & debunce information & rst state

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_DBG_conn_hif_on_misc_debug_ADDR CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_DBG_ADDR
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_DBG_conn_hif_on_misc_debug_MASK 0xFFFFFFFF                // conn_hif_on_misc_debug[31..0]
#define CONN_HOST_CSR_TOP_CONN_HIF_ON_MISC_DBG_conn_hif_on_misc_debug_SHFT 0

/* =====================================================================================

  ---CONN_HIF_BUSY_DEBUG (0x18060000 + 0x0290)---

    conn_hif_busy_debug[9..0]    - (RO) [CONN_HIF_BUSY_DBG]
                                     Internal hw status - conn_infra_bus_bridge_idle_signal
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_CONN_HIF_BUSY_DEBUG_conn_hif_busy_debug_ADDR CONN_HOST_CSR_TOP_CONN_HIF_BUSY_DEBUG_ADDR
#define CONN_HOST_CSR_TOP_CONN_HIF_BUSY_DEBUG_conn_hif_busy_debug_MASK 0x000003FF                // conn_hif_busy_debug[9..0]
#define CONN_HOST_CSR_TOP_CONN_HIF_BUSY_DEBUG_conn_hif_busy_debug_SHFT 0

/* =====================================================================================

  ---MONFLAG_DBG (0x18060000 + 0x0294)---

    conn_off_test_do[31..0]      - (RO) [CONN_OFF_MON_FLAG]
                                     connsys monitor debug flag.  It can select by conn_monflag_on.
                                     conn_monflag debug setting should reference to monflag programming guide.

 =====================================================================================*/
#define CONN_HOST_CSR_TOP_MONFLAG_DBG_conn_off_test_do_ADDR    CONN_HOST_CSR_TOP_MONFLAG_DBG_ADDR
#define CONN_HOST_CSR_TOP_MONFLAG_DBG_conn_off_test_do_MASK    0xFFFFFFFF                // conn_off_test_do[31..0]
#define CONN_HOST_CSR_TOP_MONFLAG_DBG_conn_off_test_do_SHFT    0

#ifdef __cplusplus
}
#endif

#endif // __CONN_HOST_CSR_TOP_REGS_H__
